资 源 简 介
DM54LS190/DM74LS190, DM54LS191/DM74LS191Synchronous 4-Bit Up/Down Counters with Mode ControlGeneral DescripTIonThese circuits are synchronous, reversible, up/down counters.The LS191 is a 4-bit binary counter and the LS190 is aBCD counter. Synchronous operaTIon is provided by havingall flip-flops clocked simultaneously, so that the outputschange simultaneously when so instructed by the steeringlogic. This mode of operaTIon eliminates the output counTIngspikes normally associated with asynchronous (ripple clock)counters.The outputs of the four master-slave flip-flops are triggeredon a low-to-high level transition of the clock input, if theenable input is low. A high at the enable input inhibits counting.Level changes at either the enable input or the down/up input should be made only when the clock input is high.The direction of the count is determined by the level of thedown/up input. When low, the counter counts up and whenhigh, it counts down.These counters are fully programmable; that is, the outputsmay be preset to either level by placing a low on the loadinput and entering the desired data at the data inputs. Theoutput will change independent of the level of the clock input.This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with thepreset inputs.The clock, down/up, and load inputs are buffered to lowerthe drive requirement; which significantly reduces the numberof clock drivers, etc., required for long parallel words.Two outputs have been made available to perform the cascadingfunction: ripple clock and maximum/minimum count.The latter output produces a high-level output pulse with aduration approximately equal to one complete cycle of theclock when the counter overflows or underflows. The rippleclock output produces a low-level output pulse equal inwidth to the low-level portion of the clock input when anoverflow or underflow condition exists. The counters can beeasily cascaded by feeding the ripple clock output to theenable input of the succeeding counter if parallel clocking isused, or to the clock input if parallel enabling is used. Themaximum/minimum count output can be used to accomplishlook-ahead for high-speed operation.
