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54LS112/DM54LS112A/DM74LS112ADual NegaTIve-Edge-Triggered Master-SlaveJ-K Flip-Flops with Preset, Clear,and Complementary OutputsGeneral DescripTIonThis device contains two independent negaTIve-edge-triggeredJ-K flip-flops with complementary outputs. The J andK data is processed by the flip-flop on the falling edge of theclock pulse. The clock triggering occurs at a voltage leveland is not directly related to the transiTIon time of the fallingedge of the clock pulse. Data on the J and K inputs may bechanged while the clock is high or low without affecting theoutputs as long as the setup and hold times are notviolated. A low logic level on the preset or clear inputs willset or reset the outputs regardless of the logic levels of theother inputs.FeaturesY Alternate Military/Aerospace device (54LS112) is available.Contact a National Semiconductor Sales Office/Distributor for specifications.
