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54LS194A/DM74LS194A 4-BitBidirecTIonal Universal Shift RegisterGeneral DescripTIonThis bidirecTIonal shift register is designed to incorporatevirtually all of the features a system designer may want in ashift register; they feature parallel inputs, parallel outputs,right-shift and left-shift serial inputs, operaTIng-mode-controlinputs, and a direct overriding clear line. The register hasfour distinct modes of operation, namely:Parallel (broadside) loadShift right (in the direction QA toward QD)Shift left (in the direction QD toward QA)Inhibit clock (do nothing)Synchronous parallel loading is accomplished by applyingthe four bits of data and taking both mode control inputs, S0and S1, high. The data is loaded into the associated flipflopsand appear at the outputs after the positive transitionof the clock input. During loading, serial data flow is inhibited.Shift right is accomplished synchronously with the risingedge of the clock pulse when S0 is high and S1 is low.Serial data for this mode is entered at the shift-right datainput. When S0 is low and S1 is high, data shifts left synchronouslyand new data is entered at the shift-left serialinput.Clocking of the flip-flop is inhibited when both mode controlinputs are low.FeaturesY Parallel inputs and outputsY Four operating modes:Synchronous parallel loadRight shiftLeft shiftDo nothingY Positive edge-triggered cl
