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54LS109/DM54LS109A/DM74LS109ADual PosiTIve-Edge-Triggered J-K Flip-Flopswith Preset, Clear, and Complementary OutputsGeneral DescripTIonThis device contains two independent posiTIve-edge-triggeredJ-K flip-flops with complementary outputs. The J andK data is accepted by the flip-flop on the rising edge of theclock pulse. The triggering occurs at a voltage level and isnot directly related to the transiTIon time of the rising edge ofthe clock. The data on the J and K inputs may be changedwhile the clock is high or low as long as setup and holdtimes are not violated. A low logic level on the preset orclear inputs will set or reset the outputs regardless of thelogic levels of the other inputs.FeaturesY Alternate Military/Aerospace device (54LS109) is available.Contact a National Semiconductor Sales Office/Distributor for specifications
