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SN74F175,pdf(Quadruple D-Type

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  • 上传时间:2021-08-08
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  • 标      签: Flip-Flop

资 源 简 介

This posiTIve-edge-triggered flip-flop uTIlizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR) input. InformaTIon at the data (D) inputs meeTIng setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
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