资 源 简 介
These octal transparent D-type latches with 3-state outputs are designed specifically for driving highly capaciTIve or relaTIvely low-impedance loads. They are parTIcularly suitable for implemenTIng buffer registers, I/O ports, bidirectional bus drivers, and working registers.
When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse of the levels at the D inputs.
A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
