资 源 简 介
These 8-bit latches feature 3-state outputs designed specifically for driving highly capaciTIve or relaTIvely low-impedance loads. The devices are parTIcularly suitable for implemenTIng buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D Inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
