资 源 简 介
The SN65LVDS311 serializer transmits 27 parallel input data over 1, 2, or 3 serial output links. The device pinout is opTImized to interface with the OMAP3630 applicaTIon processor. The device loads a shift register with the 24 pixel bits and 3 control bits from the parallel CMOS input interface. The data are latched into the device by the pixel clock, PCLK. In addiTIon to the 27 bits, the device adds a parity bit and two reserved bits for a total number of 30 serial bits. The parity bit allows a receiver to detect single-bit errors. Odd parity is implemented.
The serial shift register is uploaded through 1, 2, or 3 serial outputs at 30, 15, or 10 TImes the pixel clock data rate. A copy of the pixel clock is output on an additional differential output.
