资 源 简 介
MM54HC137/MM74HC137 3-to-8 LineDecoder With Address Latches(Inverted Output)General DescripTIonThis device uTIlizes advanced silicon-gate CMOS technology,to implement a three-to-eight line decoder with latcheson the three address inputs. When GL goes from low tohigh, the address present at the select inputs (A, B and C) isstored in the latches. As long as GL remains high no addresschanges will be recognized. Output enable controls,G1 and G2, control the state of the outputs independently ofthe select or latch-enable inputs. All of the outputs are highunless G1 is high and G2 is low. The HC137 is ideally suitedfor the implementaTIon of glitch-free decoders in stored-addressapplicaTIons in bus oriented systems.The 54HC/74HC logic family is speed, function and pin-outcompatible with the standard 54LS/74LS logic family. Allinputs are protected from damage due to static discharge bydiodes to VCC and ground.FeaturesY Typical propagation delay: 20 nsY Wide supply range: 2±6VY Latched inputs for easy interfacing.Y Fanout of 10 LS-TTL loads.
