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MM54HC190/MM74HC190 SynchronousDecade Up/Down Counters with ModeControl MM54HC191/MM74HC191Synchronous Binary Up/Down Counterswith Mode ControlGeneral DescripTIonThese high speed synchronous counters uTIlize advancedsilicon-gate CMOS technology. They possess the high noiseimmunity and low power consumpTIon of CMOS technology,along with the speeds of low power Schottky TTL.These circuits are synchronous, reversible, up/down counters.The MM54HC191/MM74HC191 are 4-bit binary countersand the MM54HC190/MM74HC190 are BCD counters.Synchronous operaTIon is provided by having all flip-flopsclocked simultaneously, so that the outputs change simultaneouslywhen so instructed by the steering logic. This modeof operation eliminates the output counting spikes normallyassociated with asynchronous (ripple clock) counters.The outputs of the four master-slave flip-flops are triggeredon a low-to-high level transition of the clock input, if theenable input is low. A high at the enable input inhibits counting.The direction of the count is determined by the level ofthe down/up input. When low, the counter counts up andwhen high, it counts down.These counters are fully programmable; that is, the outputsmay be preset to either level by placing a low on the loadinput and entering the desired data at the data inputs. Theoutput will change independent of the level of the clock input.This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with thepreset inputs.Two outputs have been made available to perform the cascadingfunction: ripple clock and maximum/minimum count.The latter output produces a high-level output pulse with aduration approximately equal to one complete cycle of theclock when the counter overflows or underflows. The rippleclock output produces a low-level output pulse equal inwidth to the low-level portion of the clock input when anoverflow or underflow condition exists. The counters can beeasily cascaded by feeding the ripple clock output to theenable input of the succeeding counter if parallel clocking isused, or to the clock input if parallel enabling is used. Themaximum/minimum count output can be used to accomplishlook-ahead for high-speed operation.
