资 源 简 介
1.0 GENERAL FEATURES ................ 11.1 Functional Overview ............... 21.2 CAN Controller ..................... 31.3 RAM ................................ 31.4 CPU Interface Logic ................. 31.5 Clockout ............................ 31.6 Two 8-Bit Ports ...................... 32.0 PACKAGE DIAGRAM/PIN OUT ..... 43.0 PIN DESCRIPTION ................ 53.1 Hardware Reset ..................... 83.2 Software Initialization .............. 84.0 FUNCTIONAL DESCRIPTION ....... 84.1 82527 Address Map .............. 94.2 Control Register (00H) .............. 94.3 Status Register (01H) ................104.4 CPU Interface Register (02H) ...... 124.5 Clocking Description ................ 134.6 High Speed Read Register(04±05H) .......................... 134.7 Global Mask - Standard Register(06±07H) ............................ 144.8 Global Mask - Extended Register(08±0BH) ............................ 144.9 Acceptance FilteringImplications ........................... 154.10 Message 15 Mask Register(0C±0FH) ............................... 154.11 CLKOUT Register (1FH) ........... 154.12 Bus Configuration Register(2FH) .......................... 164.13 Bit Timing Overview .............. 164.14 Bit Timing Registers(3FH, 4FH) ................................. 184.15 Comparison of 82526 and 82527Bit Timing Calculations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 194.16 Interrupt Register (5FH) ......... 194.17 Serial Reset Address (FFH) ....... 204.18 82527 Message Objects ............ 204.19 Control 0 and Control 1Registers ................................ 214.20 Arbitration 0, 1, 2, 3 Registers .... 23CONTENTS PAGE4.21 Message ConfigurationRegister ............................ 244.22 Data Bytes ..................... 244.23 Special Treatment of MessageObject 15 ........................... 245.0 PORT REGISTERS .................. 256.0 SERIAL RESET ADDRESS (FFH) ...... 267.0 FLOW DIAGRAMS ................... 267.1 82527 Handling of MessageObjects 1-14 (Direction eTransmit) ........................... 277.2 82527 Handling of MessageObjects 1-14 (Direction eReceive) ............................ 287.3 CPU Handling of Message Object15 (Direction e Receive) ............ 297.4 CPU Handling of Message Objects1±14 (Direction e Transmit) ........ 307.5 CPU Handling of Message Objects1±14 (Direction e Receive) ......... 318.0 CPU Interface Logic ............. 328.1 Serial Control Byte ............. 349.0 82527 FRAME TYPES ............... 359.1 Data Frame ...................... 359.2 Remote Frame .................... 369.3 Error Frame ..................... 369.4 Overload Frame .................. 379.5 Coding/Decoding ................. 389.6 Arbitration ..................... 3810.0 ERROR DETECTION ANDCONFINEMENT ......................... 3910.1 Bit Error ...................... 3910.2 Bit Stuffing Error ............. 3910.3 CRC Error ...................... 3910.4 Form Error ......................3910.5 Error Detection Capabilities ... 4010.6 Error Confinement .............. 4010.7 82527 States With Respect to theSerial Bus .......................... 4011.0 SAMPLE PROGRAM ................. 41
