资 源 简 介
1.0 INTRODUCTION .................................................................... 31.1 Interface Suggestions .................................................................... 11.2 Top 6 Issues .................................................................... 12.0 CPU INTERFACE MODES .................................................................... 13.0 CLOCKING STRUCTURE .....................................................................14.0 INTERFACING SCHEMATICS FOR MODE 3 ASYNCHRONOUS ................. 25.0 PAL DESCRIPTION .................................................................... 35.1 The CLK2 and PH1 Signals .....................................................................45.2 The Interrupt Signal to the Intel386TM Microprocessor .................................................................... 45.3 The Intel386TM Microprocessor W/RÝ Signal .................................................................... 45.4 The READYÝ Signal .............................................. 45.5 The CSÝ Signal to the 82527 .................................................................... 46.0 TIMING CONSIDERATIONS .................................................................... 66.1 Read Cycles .................................................................... 66.2 Write Timings .................................................................... 87.0 C-PROGRAM FOR INITIALIZING THE 82527 ............................................................... 9
