资 源 简 介
The ’LV273A devices are octal D-type flip-flops designed for 2-V to 5.5-V VCC operaTIon.
These devices are posiTIve-edge-triggered flip-flops with direct clear (CLR) input. InformaTIon at the data (D) inputs meeTIng the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
