资 源 简 介
These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability.
The edge-triggered flip-flops enter the data on the low-to-high transiTIon of the clock (CLK) input when the enable () input is low. Data can be read back onto the data inputs by taking the read () input low, in addiTIon to having low. When EN is high, both the read-back and write modes are disabled. TransiTIons on should only be made with CLK high to prevent false clocking.
The polarity of the Q outputs can be controlled by the polarity (T/C) input. When T/C is high, Q is the same as is stored in the flip-flops.
