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PLB Block RAM(BRAM)接口控制器

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  • 标      签: PLB BRAM

资 源 简 介

The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus). This controller supports the PLB V3.4 byte enable architecture.Any access size up to the width of the PLB data bus ispermitted. The PLB BRAM Interface Controller is the interfacebetween the PLB and the bram_block peripheral. ABRAM memory subsystem consists of the controller alongwith the actual BRAM components that are included in thebram_block peripheral. If the text-based MicroprocessorHardware Specification (MHS) file is used for design entry,then the bram controller and bram_block must both beexplicitly instantiated.
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