Power-constrained Testing of V

Increased levels of chip integraTIon combined with physical limitaTIons of heatremoval devices, cooling mechanisms and battery capacity, have establishedenergy-efficiency as an important design objecTIve in the implementaTIon flow ofmodern electronic products. To meet these low energy objectives, new lowpower techniques, including circuits, architectures, methodologies, algorithmsand computer-aided design tool flows, have emerged.If the integration trend continues in the coming decade, i.e. transistors on leadmicroprocessors double every two years, die size grows by 14% every two years,supply voltage scales meagerly, and frequency doubles every two years, thenwhat would happen to power and energy? Expected power consumption of suchmicroprocessors, which goes beyond 100watts today, will grow by an order ofmagnitude every two years reaching 10Kwatts in 2008. It is clear that excessivepower usage may become prohibitive and total power consumption will be alimiting factor in the near future. These two factors will become even morecritical for lower performance applications, such as in portable products, wherelow power techniques becomes a necessity. Planning for power need to beincorporated into the design flow of such systems.Since most of the existing low power techniques aim to reduce the switchingactivity during the functional operation, they may conflict with the state-of-theart manufacturing test flow.In fact, power management is not limited to the design space only, testing chipswith high power consumption is a major problem too. For example, a complexchip may consume three or four times higher power during testing whencompared to its functional operation. This leads to a reliability problem sinceoverheating can cause destructive test. An additional concern for testing lowpower circuits is caused by the interaction between the existing design-for-testmethods and voltage drop on power/ground networks. Due to high circuitactivity when employing scan or built-in self-test, the voltage drop which occursonly during test will cause some good circuits to fail the testing process, thusleading to unnecessary manufacturing yield loss. Therefore, accounting forpower dissipation during test is emerging as a necessary step in theimplementation flow, which will ultimately influence both the quality and thecost of test. To keep the pace with the low power design practices, it is essential that the emerging system-on-a-chip test methodologies regard power-constrained testing as an important parameter when establishing the manufacturing test requirements. Today, we have started to see certain embedded test solutions that are designed with infrastructure IP to perform power management on-chip. Withthe increasing use of embedded cores from third party IP providers, it is expectedthat power-constrained test solutions be implemented at the cores level by thethird party IP providers.This book is the first comprehensive book that covers all aspects of powerconstrained test solutions. It is a reflection of authors’ own research and also a survey of the major contributions in this domain. I strongly recommend this book to all engineers involved in design and test of system-on-chip, who want tounderstand the impact of power on test and design-for-test.