资 源 简 介
The ADCLK846 is a 1.2 GHz/250 MHz， LVDS/CMOS， fanout buffer opTImized for low jitter and low power operaTIon. Possible configuraTIons range from 6 LVDS to 12 CMOS outputs， including combinaTIons of LVDS and CMOS outputs. Two control lines are used to determine whether fixed blocks of outputs are LVDS or CMOS outputs. The clock input accepts various types of single-ended and differential logic levels including LVPECL， LVDS， HSTL， CML， and CMOS. Table 8 provides interface options for each type of connection. The SLEEP pin enables a sleep mode to power down the device. This device is available in a 24-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C.
