资 源 简 介
Section 1 Introduction1.1 Integer Unit User Programming Model . . . . . . 1-21.1.1 Data Registers (D7 – D0) . . . . 1-21.1.2 Address Registers (A7 – A0) . . 1-21.1.3 Program Counter . . 1-31.1.4 Condition Code Register . . . . . 1-31.2 Floating-Point Unit User Programming Model 1-41.2.1 Floating-Point Data Registers (FP7 – FP0) . 1-41.2.2 Floating-Point Control Register (FPCR) . . . 1-51.2.2.1 Exception Enable Byte . . . . . 1-51.2.2.2 Mode Control Byte . . . . . . . . 1-51.2.3 Floating-Point Status Register (FPSR) . . . . 1-51.2.3.1 Floating-Point Condition Code Byte . . . . . 1-51.2.3.2 Quotient Byte . . . 1-61.2.3.3 Exception Status Byte. . . . . . 1-61.2.3.4 Accrued Exception Byte . . . . 1-71.2.4 Floating-Point Instruction Address Register (FPIAR) 1-81.3 Supervisor Programming Model . 1-81.3.1 Address Register 7 (A7) . . . . 1-101.3.2 Status Register . . 1-101.3.3 Vector Base Register (VBR) . 1-111.3.4 Alternate Function Code Registers (SFC and DFC) 1-111.3.5 Acu Status Register (MC68EC030 only) . . 1-111.3.6 Transparent Translation/access Control Registers . 1-121.3.6.1 Transparent Translation/access Control Register Fields for theM68030 . . . 1-121.3.6.2 Transparent Translation/access Control Register Fields for theM68040 . . . 1-131.4 Integer Data Formats . . . . . . . . 1-141.5 Floating-Point Data Formats . . 1-151.5.1 Packed Decimal Real Format 1-151.5.2 Binary Floating-Point Formats 1-161.6 Floating-Point Data Types . . . . 1-171.6.1 Normalized Numbers . . . . . . . 1-181.6.2 Denormalized Numbers . . . . . 1-181.6.3 Zeros . . . . . . 1-191.6.4 Infinities . . . . 1-191.6.5 Not-A-Numbers . . 1-191.6.6 Data Format and Type Summary . . . . . . . 1-201.7 Organization of Data in Registers . . . . . . . . 1-251.7.1 Organization of Integer Data Formats in Registers . 1-251.7.2 Organization of Integer Data Formats in Memory . . 1-271.7.3 Organization of Fpu Data Formats in Registers and Memory . . . . . . 1-30Section 2 Addressing Capabilities2.1 Instruction Format . . 2-12.2 Effective Addressing Modes . . . . 2-42.2.1 Data Register Direct Mode . . . 2-52.2.2 Address Register Direct Mode . 2-52.2.3 Address Register Indirect Mode 2-52.2.4 Address Register Indirect with Postincrement Mode . 2-62.2.5 Address Register Indirect with Predecrement Mode . 2-72.2.6 Address Register Indirect with Displacement Mode . 2-82.2.7 Address Register Indirect with Index (8-Bit Displacement) Mode . . . . 2-92.2.8 Address Register Indirect with Index (Base Displacement) Mode. . . 2-102.2.9 Memory Indirect Postindexed Mode . . . . . 2-112.2.10 Memory Indirect Preindexed Mode . . . . . . 2-122.2.11 Program Counter Indirect with Displacement Mode 2-132.2.12 Program Counter Indirect with Index (8-Bit Displacement) Mode . . . 2-142.2.13 Program Counter Indirect with Index (Base Displacement) Mode. . . 2-152.2.14 Program Counter Memory Indirect Postindexed Mode . . 2-162.2.15 Program Counter Memory Indirect Preindexed Mode . . . 2-172.2.16 Absolute Short Addressing Mode . . . . . . . 2-182.2.17 Absolute Long Addressing Mode . . . . . . . . 2-182.2.18 Immediate Data . . 2-192.3 Effective Addressing Mode Summary . . . . . 2-192.4 Brief Extension Word Format Compatibility . 2-212.5 Full Extension Addressing Modes . . . . . . . . 2-222.5.1 No Memory Indirect Action Mode . . . . . . . 2-242.5.2 Memory Indirect Modes . . . . . 2-252.5.2.1 Memory Indirect with Preindex . . . . . . . . 2-252.5.2.2 Memory Indirect with Postindex . . . . . . . 2-262.5.2.3 Memory Indirect with Index Suppressed. 2-272.6 Other Data Structures . . . . . . . 2-282.6.1 System Stack 2-282.6.2 Queues . . . . 2-29Section 3 Instruction Set Summary3.1 Instruction Summary 3-13.1.1 Data Movement Instructions . . 3-53.1.2 Integer Arithmetic Instructions . 3-63.1.3 Logical Instructions 3-83.1.4 Shift and Rotate Instructions . . 3-8
3.1.5 Bit Manipulation Instructions . 3-103.1.6 Bit Field Instructions . . . . . . . 3-103.1.7 Binary-Coded Decimal Instructions . . . . . . 3-113.1.8 Program Control Instructions . 3-113.1.9 System Control Instructions . . 3-123.1.10 Cache Control Instructions (MC68040) . . . 3-143.1.11 Multiprocessor Instructions . . 3-143.1.12 Memory Management Unit (MMU) Instructions . . . . 3-153.1.13 Floating-Point Arithmetic Instructions . . . . 3-153.2 Integer Unit Condition Code Computation . . 3-173.3 Instruction Examples . . . . . . . . 3-203.3.1 Using the Cas and Cas2 Instructions . . . . 3-203.3.2 Using the Moves Instruction . 3-203.3.3 Nested Subroutine Calls . . . . 3-203.3.4 Bit Field Instructions . . . . . . . 3-203.3.5 Pipeline Synchronization with the Nop Instruction . . 3-213.4 Floating-Point Instruction Details 3-213.5 Floating-Point Computational Accuracy . . . . 3-233.5.1 Intermediate Result . . . . . . . . 3-243.5.2 Rounding the Result . . . . . . . 3-253.6 Floating-Point Postprocessing . 3-273.6.1 Underflow, Round, Overflow . 3-283.6.2 Conditional Testing . . . . . . . . 3-283.7 Instruction Descriptions . . . . . . 3-32Section 4 Integer InstructionsSection 5 Floating Point InstructionsSection 6 Supervisor (Privileged) InstructionsSection 7 CPU32 InstructionsSection 8 Instruction Format Summary8.1 Instruction Format 8.1 Instruction Format . . 8-18.1.1 Coprocessor ID Field . . . . . . . . 8-18.1.2 Effective Address Field . . . . . . 8-18.1.3 Register/Memory Field . . . . . . 8-18.1.4 Source Specifier Field . . . . . . . 8-18.1.5 Destination Register Field . . . . 8-28.1.6 Conditional Predicate Field . . . 8-28.1.7 Shift and Rotate Instructions . . 8-28.1.7.1 Count Register Field . . . . . . . 8-28.1.7.2 Register Field . . . 8-28.1.8 Size Field . . . . 8-48.1.9 Opmode Field 8-48.1.10 Address/Data Field 8-48.2 Operation Code Map 8-4Appendix AProcessor Instruction SummaryA.1 MC68000, MC68008, MC68010 Processors A-12A.1.1 M68000, MC68008, and MC68010 Instruction Set . A-12A.1.2 MC68000, MC68008, and MC68010 Addressing Modes A-16A.2 MC68020 Processors . . . . . . . . A-17A.2.1 MC68020 Instruction Set . . . . A-17A.2.2 MC68020 Addressing Modes A-20A.3 MC68030 Processors . . . . . . . . A-21A.3.1 MC68030 Instruction Set . . . . A-21A.3.2 MC68030 Addressing Modes A-24A.4 MC68040 Processors . . . . . . . . A-25A.4.1 MC68040 Instruction Set . . . . A-25A.4.2 MC68040 Addressing Modes A-29A.5 MC68881/MC68882 Coprocessors . . . . . . . A-30A.5.1 MC68881/MC68882 Instruction Set . . . . . A-30A.5.2 MC68881/MC68882 Addressing Modes . . A-31A.6 MC68851 Coprocessors . . . . . . A-31A.6.1 MC68851 Instruction Set . . . . A-31A.6.2 MC68851 Addressing Modes A-31Appendix B Exception Processing ReferenceB.1 Exception Vector Assignments for the M68000 Family B-1B.2 Exception Stack Frames . . . . . . B-3B.3 Floating-Point Stack Frames . . B-10Appendix C S-Record Output FormatC.1 S-Record Content . . . C-1C.2 S-Record Types C-2C.3 S-Record Creation . . C-3
