资 源 简 介
This dual posiTIve-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operaTIon.
When data at the data (D) input meets the setup TIme requirement, the data is transferred to the Q output on the posiTIve-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
