资 源 简 介
This single D-type latch is designed for 1.65-V to 5.5-V VCC operaTIon.
The SN74LVC1G374 features a 3-state output designed specifically for driving highly capaciTIve or relaTIvely low-impedance loads. This device is parTIcularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
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On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input.
A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
