资 源 简 介
The ATmega64 provides the following features: 64K bytes of In-System ProgrammableFlash with Read-While-Write capabiliTIes, 2K bytes EEPROM, 4K bytes SRAM, 53 gen-eral purpose I/O lines, 32 general purpose working registers, Real TIme Counter (RTC),four flexible TImer/Counters with compare modes and PWM, two USARTs, a byte ori-ented Two-wire Serial Interface, an 8-channel, 10-bit ADC with opTIonal differential inputstage with programmable gain, programmable Watchdog Timer with internal Oscillator,an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used foraccessing the On-chip Debug system and programming, and six software selectablepower saving modes. The Idle mode stops the CPU while allowing the SRAM,Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all otherchip functions until the next interrupt or Hardware Reset. In Power-save mode, the asyn-chronous timer continues to run, allowing the user to maintain a timer base while therest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and allI/O modules except asynchronous timer and ADC, to minimize switching noise duringADC conversions. In Standby mode, the crystal/resonator Oscillator is running while therest of the device is sleeping. This allows very fast start-up combined with low powerconsumption. In Extended Standby mode, both the main Oscillator and the asynchro-nous timer continue to run.
