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SN74ALVCHR162601,pdf(18-BIT UN

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  • 上传时间:2021-09-03
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  • 标      签: transceive

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This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operaTIon. The SN74ALVCHR16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. Data flow in each direcTIon is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transiTIon of CLKAB.
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