资 源 简 介
This 18-bit (dual-octal) noninverTIng registered transceiver is designed for 1.65-V to 3.6-V VCC operaTIon.
The SN74LVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver, or it can generate/check parity from the two 8-bit data buses in either direcTIon.
The SN74LVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direcTIon of data flow is controlled by output-enable (OEAB and OEBA) inputs. When SEL is low, the parity functions are enabled.
