资 源 简 介
The AD5382 is a complete， single-supply， 32-channel， 14-bit denseDAC® available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operaTIon. The AD5382 includes an internal software-selectable 1.25 V/2.5 V， 10 ppm/°C reference， an on-chip channel monitor funcTIon that mulTIplexes the analog outputs to a common MON_OUT pin for external monitoring， and an output amplifier boost mode that allows opTImization of the amplifier slew rate. The AD5382 contains a double-buffered parallel interface， which features a 20 ns WR pulse width， an SPI-， QSPI-， MICROWIRE-， DSP-compatible serial interface with interface speeds in excess of 30 MHz and an I2 C®-compatible interface that supports a 400 kHz data transfer rate. An input register followed by a DAC register provides double buffering， allowing the DAC outputs to be updated independently or simultaneously using the LDAC input. Each channel has a programmable gain and offset adjust register that allows the user to fully calibrate any DAC channel. Power consumption is typically 0.25 mA per channel when operating with boost mode disabled.
