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CY74FCT377AT,pdf(8-Bit Registe

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The x92FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE) input is low. The register is fully edge triggered. The state of each D input at one setup TIme before the low-to-high clock transiTIon is transferred to the corresponding flip-flop output (O). CE must be stable only one setup TIme prior to the low-to-high clock transiTIon for predictable operation. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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