资 源 简 介
fpga reference design Offer:QuickLogic
PCI Arbiter:Files: APPSpci arbiterpci_arb.exePCI Master/Target Design:Files: APPSPCIMASTER*.*Top Level Design: TOP.SCHSimulation Test Fixture: TOP.TF (Verilog HDL Format)Schematic-Based Design with Verilog Sub-BlocksUtilization583 of 768 logic cells, QL24x32B pASIC 1 device480 of 672 logic cells, QL2009 pASIC 2 device123 pins (recommended pinout available, see synthesis constraint fileTOP.SC)OverviewThis application note describes a fully PCI-compliant Master/Slaveinterface. It utilizes thePCI burst transfer mode for transfers at high speed, up to 67 MBytes persecond. Although itis designed to interface the Seeq 80C300 Ethernet Data Link Controllerto the PCI bus, it canbe easily modified to interface with other peripherals. Data is transferredbetween SystemMemory and the Ethernet controller in bursts of eight using Master ModeDMA. Internal80C300 programming registers are mapped into host memory space andare accessed usingslave mode.
