资 源 简 介
The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access TImes. This device is designed for 3-V to 3.6-V VCC operaTIon. Two devices can be configured for bidirecTIonal data buffering without addiTIonal logic.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN, OE1, and OE2 levels.
