资 源 简 介
The SN74V263, SN74V273, SN74V283, and SN74V293 are excepTIonally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.
There is flexible ×9/×18 bus matching on both read and write ports.
The period required by the retransmit operaTIon is fixed and short.
The first-word data-latency period, from the TIme the first word is written to an empty FIFO to the TIme it can be read, is fixed and short.
These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during the master-reset cycle.
