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54LS161A/DM54LS161A/DM74LS161A,54LS163A/DM54LS163A/DM74LS163ASynchronous 4-Bit Binary CountersGeneral DescripTIonThese synchronous, presettable counters feature an internalcarry look-ahead for applicaTIon in high-speed counTIngdesigns. The LS161A and LS163A are 4-bit binary counters.The carry output is decoded by means of a NOR gate, thusprevenTIng spikes during the normal counting mode of operation.Synchronous operation is provided by having all flipflopsclocked simultaneously so that the outputs change coincidentwith each other when so instructed by the countenableinputs and internal gating. This mode of operationeliminates the output counting spikes which are normallyassociated with asynchronous (ripple clock) counters. Abuffered clock input triggers the four flip-flops on the rising(positive-going) edge of the clock input waveform.These counters are fully programmable; that is, the outputsmay be preset to either level. As presetting is synchronous,setting up a low level at the load input disables the counterand causes the outputs to agree with the setup data afterthe next clock pulse, regardless of the levels of the enableinput. The clear function for the LS161A is asynchronous;and a low level at the clear input sets all four of the flip-flopoutputs low, regardless of the levels of clock, load, or enableinputs. The clear function for the LS163A is synchronous;and a low level at the clear inputs sets all four of theflip-flop outputs low after the next clock pulse, regardless ofthe levels of the enable inputs. This synchronous clear allowsthe count length to be modified easily, as decoding themaximum count desired can be accomplished with one externalNAND gate. The gate output is connected to the clearinput to synchronously clear the counter to all low outputs.The carry look-ahead circuitry provides for cascading countersfor n-bit synchronous applications without additionalgating. Instrumental in accomplishing this function are twocount-enable inputs and a ripple carry output.Both count-enable inputs (P and T) must be high to count,and input T is fed forward to enable the ripple carry output.The ripple carry output thus enabled will produce a high-leveloutput pulse with a duration approximately equal to thehigh-level portion of the QA output. This high-level overflowripple carry pulse can be used to enable successive cascadedstages. High-to-low level transitions at the enable P or Tinputs may occur, regardless of the logic level of the clock.These counters feature a fully independent clock circuit.Changes made to control inputs (enable P or T or load) thatwill modify the operating mode have no effect until clockingoccurs. The function of the counter (whether enabled, disabled,loading, or counting) will be dictated solely by theconditions meeting the stable set-up and hold times.
