资 源 简 介
This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is designed for general-purpose storage applicaTIons in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demulTIplexers. This is a mulTI-funcTIonal device capable of storing single-line data in eight addressable latches with 3-to-8 decoding or demultiplexing mode active-low DMOS outputs.
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch. The addressed DMOS transistor output inverts the data input with all unaddressed DMOS-transistor outputs remaining in their previous states.
