资 源 简 介
54LS174/DM54LS174/DM74LS174,54LS175/DM54LS175/DM74LS175 Hex/Quad D Flip-Flops with Clear
General DescripTIon
These posiTIve-edge-triggered flip-flops uTIlize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (175) versions feature complementary
outputs from each flip-flop.
InformaTIon at the D inputs meeting the setup time requirements
is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the high or low level, the D input signal has no effect
at the output.
Features
Y LS174 contains six flip-flops with single-rail outputs
Y LS175 contains four flip-flops with double-rail outputs
Y Buffered clock and direct clear inputs
Y Individual data input to each flip-flop
Y Applications include:
Buffer/storage registers
Shift registers
Pattern generators
Y Typical clock frequency 40 MHz
Y Typical power dissipation per flip-flop 14 mW
Y Alternate Military/Aerospace device (54LS174,
54LS175) is available. Contact a National Semiconductor
Sales Office/Distributor for specifications.
