资 源 简 介
Audience xxixOrganization.. xxixSuggested ReadingxxxConventions xxxiiiAcronyms and Abbreviations . xxxivTerminology Conventions .. xxxviiChapter 1Overview1.1 Overview. 1-11.1.1 Features 1-21.1.2 System Design and Programming Considerations. 1-71.1.2.1 Hardware Features .. 1-71.1.2.1.1 Replacement of XATS Signal by CSE1 Signal 1-71.1.2.1.2 Addition of Half-Clock Bus Multipliers 1-71.1.2.2 Software Features ... 1-81.1.2.2.1 16-Kbyte Instruction and Data Caches .. 1-81.1.2.2.2 Clock Configuration Available in HID1 Register .. 1-81.1.2.2.3 Performance Enhancements 1-81.1.3 Instruction Unit . 1-91.1.3.1 Instruction Queue and Dispatch Unit .. 1-91.1.3.2 Branch Processing Unit (BPU) 1-91.1.4 Independent Execution Units 1-101.1.4.1 Integer Unit (IU) ... 1-101.1.4.2 Floating-Point Unit (FPU) 1-101.1.4.3 Load/Store Unit (LSU) .. 1-111.1.4.4 System Register Unit (SRU). 1-111.1.4.5 Completion Unit ... 1-111.1.5 Memory Subsystem Support. 1-121.1.5.1 Memory Management Units (MMUs). 1-121.1.5.2 Cache Units. 1-131.1.6 Processor Bus Interface . 1-141.1.7 System Support Functions..1-141.1.7.1 Power Management..1-151.1.7.2 Time Base/Decrementer .1-151.1.7.3 IEEE 1149.1 (JTAG)/COP Test Interface1-161.1.7.4 Clock Multiplier 1-161.2 PowerPC Architecture Implementation...1-161.3 Implementation-Specific Information .1-161.3.1 Programming Model..1-171.3.1.1 Processor Version Register (PVR) ..1-181.3.1.2 Hardware Implementation Register 0 (HID0)..1-181.3.1.3 Run_N Counter Register (Run_N) ..1-191.3.1.4 General-Purpose Registers (GPRs) .1-191.3.1.5 Floating-Point Registers (FPRs)1-191.3.1.6 Condition Register (CR).1-191.3.1.7 Floating-Point Status and Control Register (FPSCR) 1-191.3.1.8 Machine State Register (MSR)..1-191.3.1.9 Segment Registers (SRs) 1-191.3.1.10 Special-Purpose Registers (SPRs)...1-201.3.1.10.1 User-Level SPRs ..1-201.3.1.10.2 Supervisor-Level SPRs .1-201.3.2 Instruction Set and Addressing Modes1-231.3.2.1 PowerPC Instruction Set and Addressing Modes1-231.3.2.1.1 PowerPC Instruction Set ...1-231.3.2.1.2 Calculating Effective Addresses .1-241.3.2.2 Implementation-Specific Instruction Set..1-251.3.3 Cache Implementation..1-251.3.3.1 PowerPC Cache Characteristics 1-251.3.3.2 Implementation-Specific Cache Implementation1-261.3.4 Exception Model .1-271.3.4.1 PowerPC Exception Model ...1-271.3.4.2 Implementation-Specific Exception Model1-291.3.5 Memory Management ..1-321.3.5.1 PowerPC Memory Management .1-321.3.5.2 Implementation-Specific Memory Management.1-321.3.6 Instruction Timing .1-331.3.7 System Interface ..1-351.3.7.1 Memory Accesses..1-361.3.7.2 Signals 1-361.3.7.3 Signal Configuration 1-382.1 Register Set ..2-12.1.1 PowerPC Register Set .2-12.1.2 Implementation-Specific Registers .2-72.1.2.1 Hardware Implementation Registers (HID0 and HID1) ..2-72.1.2.2 Data and Instruction TLB Miss Address Registers(DMISS and IMISS) 2-92.1.2.3 Data and Instruction TLB Compare Registers(DCMP and ICMP) 2-92.1.2.4 Primary and Secondary Hash Address Registers(HASH1 and HASH2) 2-102.1.2.5 Required Physical Address Register (RPA).2-112.1.2.6 Instruction Address Breakpoint Register (IABR) .2-112.1.2.7 Run_N Counter Register (Run_N)..2-122.2 Operand Conventions2-122.2.1 Floating-Point Execution Models—UISA ...2-122.2.2 Data Organization in Memory and Data Transfers .2-132.2.3 Alignment and Misaligned Accesses ..2-132.2.4 Floating-Point Operand2-142.2.5 Effect of Operand Placement on Performance.2-142.3 Instruction Set Summary..2-152.3.1 Classes of Instructions..2-162.3.1.1 Definition of Boundedly Undefined ..2-162.3.1.2 Defined Instruction Class2-162.3.1.3 Illegal Instruction Class .2-172.3.1.4 Reserved Instruction Class2-182.3.2 Addressing Modes.2-182.3.2.1 Memory Addressing.2-182.3.2.2 Memory Operands.2-182.3.2.3 Effective Address Calculation ..2-192.3.2.4 Synchronization 2-192.3.2.4.1 Context Synchronization...2-202.3.2.4.2 Execution Synchronization 2-202.3.2.4.3 Instruction-Related Exceptions ...2-202.3.3 Instruction Set Overview2-212.3.4 PowerPC UISA Instructions .2-212.3.4.1 Integer Instructions ..2-212.3.4.1.1 Integer Arithmetic Instructions ...2-222.3.4.1.2 Integer Compare Instructions2-222.3.4.1.3 Integer Logical Instructions ..2-232.3.4.1.4 Integer Rotate and Shift Instructions ...2-242.3.4.2 Floating-Point Instructions 2-252.3.4.2.1 Floating-Point Arithmetic Instructions.2-262.3.4.2.2 Floating-Point Multiply-Add Instructions2-262.3.4.2.3 Floating-Point Rounding and Conversion Instructions .2-272.3.4.2.4 Floating-Point Compare Instructions ...2-272.3.4.2.5 Floating-Point Status and Control Register Instructions.2-272.3.4.2.6 Floating-Point Move Instructions2-282.3.4.3 Load and Store Instructions...2-282.3.4.3.1 Self-Modifying Code..2-292.3.4.3.2 Integer Load and Store Address Generation 2-292.3.4.3.3 Register Indirect Integer Load Instructions..2-292.3.4.3.4 Integer Store Instructions ..2-302.3.4.3.5 Integer Load and Store with Byte-Reverse Instructions .2-312.3.4.3.6 Integer Load and Store Multiple Instructions..2-322.3.4.3.7 Integer Load and Store String Instructions...2-332.3.4.3.8 Floating-Point Load and Store Address Generation...2-342.3.4.3.9 Floating-Point Load Instructions.2-342.3.4.3.10 Floating-Point Store Instructions 2-342.3.4.4 Branch and Flow Control Instructions .2-352.3.4.4.1 Branch Instruction Address Calculation.2-362.3.4.4.2 Branch Instructions 2-362.3.4.4.3 Condition Register Logical Instructions 2-362.3.4.5 Trap Instructions2-372.3.4.6 Processor Control Instructions ..2-372.3.4.6.1 Move to/from Condition Register Instructions .2-382.3.4.7 Memory Synchronization Instructions—UISA2-382.3.5 PowerPC VEA Instructions2-392.3.5.1 Processor Control Instructions ..2-392.3.5.2 Memory Synchronization Instructions—VEA.2-402.3.5.3 Memory Control Instructions—VEA.2-412.3.5.4 External Control Instructions 2-422.3.6 PowerPC OEA Instructions2-422.3.6.1 System Linkage Instructions .2-422.3.6.2 Processor Control Instructions—OEA .2-422.3.6.2.1 Move to/from Machine State Register Instructions ...2-432.3.6.2.2 Move to/from Special-Purpose Register Instructions 2-432.3.6.3 Memory Control Instructions—OEA.2-442.3.6.3.1 Supervisor-Level Cache Management Instruction 2-442.3.6.3.2 Segment Register Manipulation Instructions ..2-452.3.6.3.3 Translation Lookaside Buffer Management Instructions2-452.3.7 Recommended Simplified Mnemonics ..2-462.3.8 Implementation-Specific Instructions .2-463.1 Instruction Cache Organization and Control3-33.1.1 Instruction Cache Organization...3-33.1.2 Instruction Cache Fill Operations 3-43.1.3 Instruction Cache Control 3-43.1.3.1 Instruction Cache Invalidation 3-43.1.3.2 Instruction Cache Disabling3-43.1.3.3 Instruction Cache Locking 3-43.2 Data Cache Organization and Control 3-53.2.1 Data Cache Organization .3-53.2.2 Data Cache Fill Operations ..3-53.2.3 Data Cache Control .3-63.2.3.1 Data Cache Invalidation...3-63.2.3.2 Data Cache Disabling.3-63.2.3.3 Data Cache Locking3-63.2.3.4 Data Cache Operations and Address Broadcasts ..3-73.2.4 Data Cache Touch Load Support 3-73.3 Basic Data Cache Operations...3-83.3.1 Data Cache Fill..3-83.3.2 Data Cache Cast-Out Operation..3-83.3.3 Cache Block Push Operation 3-83.4 Data Cache Transactions on Bus.3-83.4.1 Single-Beat Transactions .3-83.4.2 Burst Transactions.3-83.4.3 Access to Direct-Store Segments 3-93.5 Memory Management/Cache Access Mode Bits—W, I, M, and G3-103.5.1 Write-Through Attribute (W)3-113.5.2 Caching-Inhibited Attribute (I) .3-113.5.3 Memory Coherency Attribute (M) 3-123.5.4 Guarded Attribute (G) ..3-123.5.5 W, I, and M Bit Combinations ..3-133.5.5.1 Out-of-Order Execution and Guarded Memory..3-133.5.5.2 Effects of Out-of-Order Data Accesses ...3-143.5.5.3 Effects of Out-of-Order Instruction Fetches 3-143.6 Cache Coherency—MEI Protocol.3-153.6.1 MEI State Definitions ..3-153.6.2 MEI State Diagram ...3-163.6.3 MEI Hardware Considerations..3-173.6.4 Coherency Precautions.3-183.6.4.1 Coherency in Single-Processor Systems..3-183.6.5 Load and Store Coherency Summary .3-183.6.6 Atomic Memory References3-193.6.7 Cache Reaction to Specific Bus Operations.3-193.6.8 Operations Causing ARTRY Assertion ..3-213.6.9 Enveloped High-Priority Cache Block Push Operation 3-213.7 Cache Control Instructions .3-223.7.1 Data Cache Block Invalidate (dcbi) Instruction ...3-233.7.2 Data Cache Block Touch (dcbt) Instruction 3-233.7.3 Data Cache Block Touch for Store (dcbtst) Instruction 3-243.7.4 Data Cache Block Clear to Zero (dcbz) Instruction3-243.7.5 Data Cache Block Store (dcbst) Instruction 3-243.7.6 Data Cache Block Flush (dcbf) Instruction..3-243.7.7 Enforce In-Order Execution of I/O Instruction (eieio)..3-253.7.8 Instruction Cache Block Invalidate (icbi) Instruction ...3-253.7.9 Instruction Synchronize (isync) Instruction .3-253.8 Bus Operations Caused by Cache Control Instructions.3-253.9 Bus Interface..3-273.10 MEI State Transactions .3-284.1 Exception Classes ..4-24.1.1 Exception Priorities .4-74.1.2 Summary of Front-End Exception Handling..4-94.2 Exception Processing.4-104.2.1 Enabling and Disabling Exceptions.4-144.2.2 Steps for Exception Processing .4-154.2.3 Setting MSR[RI]..4-154.2.4 Returning from an Exception Handler 4-164.3 Process Switching4-164.4 Exception Latencies.4-174.5 Exception Definitions 4-174.5.1 Reset Exceptions (0x00100)4-184.5.1.1 Hard Reset and Power-On Reset .4-194.5.1.2 Soft Reset 4-204.5.2 Machine Check Exception (0x00200) .4-214.5.2.1 Machine Check Exception Enabled (MSR[ME] = 1) 4-224.5.2.2 Checkstop State (MSR[ME] = 0) 4-224.5.3 DSI Exception (0x00300)...4-234.5.4 ISI Exception (0x00400) 4-254.5.5 External Interrupt (0x00500).4-254.5.6 Alignment Exception (0x00600) 4-264.5.6.1 Integer Alignment Exceptions ..4-274.5.6.1.1 Page Address Translation Access ..4-284.5.6.2 Floating-Point Alignment Exceptions4-284.5.7 Program Exception (0x00700) ..4-294.5.7.1 IEEE Floating-Point Exception Program Exceptions 4-304.5.7.2 Illegal, Reserved, and Unimplemented InstructionsProgram Exceptions ...4-304.5.8 Floating-Point Unavailable Exception (0x00800) ..4-314.5.9 Decrementer Exception (0x00900) .4-314.5.10 System Call Exception (0x00C00)4-314.5.11 Trace Exception (0x00D00)4-324.5.11.1 Single-Step Instruction Trace Mode ..4-334.5.11.2 Branch Trace Mode..4-334.5.12 Instruction TLB Miss Exception (0x01000) 4-334.5.13 Data TLB Miss on Load Exception (0x01100)4-344.5.14 Data TLB Miss on Store Exception (0x01200)4-354.5.15 Instruction Address Breakpoint Exception (0x01300)..4-354.5.16 System Management Interrupt (0x01400) ...4-375.1 MMU Features 5-25.1.1 Memory Addressing5-35.1.2 MMU Organization.5-35.1.3 Address Translation Mechanisms 5-85.1.4 Memory Protection Facilities5-105.1.5 Page History Information...5-115.1.6 General Flow of MMU Address Translation .5-115.1.6.1 Real Addressing Mode and Block Address Translation Selection ...5-115.1.6.2 Page Address Translation Selection5-125.1.7 MMU Exceptions Summary .5-145.1.8 MMU Instructions and Register Summary ..5-175.2 Real Addressing Mode..5-205.3 Block Address Translation .5-205.4 Memory Segment Model..5-215.4.1 Page History Recording .5-215.4.1.1 Referenced Bit.5-225.4.1.2 Changed Bit.5-235.4.1.3 Scenarios for Referenced and Changed Bit Recording..5-235.4.2 Page Memory Protection5-255.4.3 TLB Description..5-255.4.3.1 TLB Organization..5-255.4.3.2 TLB Entry Invalidation ..5-275.4.4 Page Address Translation Summary ...5-285.5 Page Table Search Operation .5-305.5.1 Page Table Search Operation—Conceptual Flow5-305.5.2 Implementation-Specific Table Search Operation ..5-335.5.2.1 Resources for Table Search Operations ...5-345.5.2.1.1 Data and Instruction TLB Miss Address Registers(DMISS and IMISS)...5-365.5.2.1.2 Data and Instruction TLB Compare Registers (DCMP and ICMP).5-375.5.2.1.3 Primary and Secondary Hash Address Registers(HASH1 and HASH2)5-375.5.2.1.4 Required Physical Address Register (RPA).5-385.5.2.2 Software Table Search Operation5-385.5.2.2.1 Flow for Example Exception Handlers 5-395.5.2.2.2 Code for Example Exception Handlers 5-445.5.3 Page Table Updates ...5-505.5.4 Segment Register Updates..5-506.1 Terminology and Conventions .6-16.2 Instruction Timing Overview ...6-36.3 Timing Considerations 6-56.3.1 General Instruction Flow6-66.3.2 Instruction Fetch Timing 6-96.3.2.1 Cache Arbitration 6-96.3.2.2 Cache Hit.6-96.3.2.3 Cache Miss ..6-106.3.3 Instruction Dispatch and Completion Considerations...6-116.3.3.1 Rename Register Operation...6-126.3.3.2 Instruction Serialization .6-136.3.3.3 Execution Unit Considerations..6-146.4 Execution Unit Timings.6-146.4.1 Branch Processing Unit Execution Timing ..6-146.4.1.1 Branch Folding 6-146.4.1.2 Static Branch Prediction .6-166.4.1.2.1 Predicted Branch Timing Examples.6-166.4.2 Integer Unit Execution Timing..6-186.4.3 Floating-Point Unit Execution Timing6-186.4.4 Load/Store Unit Execution Timing .6-186.4.5 System Register Unit Execution Timing6-186.5 Memory Performance Considerations.6-186.5.1 Copy-Back Mode 6-196.5.2 Write-Through Mode 6-196.5.3 Cache-Inhibited Accesses ..6-206.6 Instruction Scheduling Guidelines 6-206.6.1 Branch, Dispatch, and Completion Unit Resource Requirements ..6-216.6.1.1 Branch Resolution Resource Requirements.6-216.6.1.2 Dispatch Unit Resource Requirements 6-216.6.1.3 Completion Unit Resource Requirements6-226.7 Instruction Latency Summary 6-227.1 Signal Configuration .7-37.2 Signal Descriptions 7-47.2.1 Address Bus Arbitration Signals.7-47.2.1.1 Bus Request (BR)—Output.7-47.2.1.2 Bus Grant (BG)—Input7-57.2.1.3 Address Bus Busy (ABB) 7-57.2.1.3.1 Address Bus Busy (ABB)—Output .7-57.2.1.3.2 Address Bus Busy (ABB)—Input.7-67.2.2 Address Transfer Start Signals7-67.2.2.1 Transfer Start (TS) ..7-67.2.2.1.1 Transfer Start (TS)—Output 7-67.2.2.1.2 Transfer Start (TS)—Input..7-77.2.3 Address Transfer Signals .7-77.2.3.1 Address Bus (A[0–31]) 7-77.2.3.1.1 Address Bus (A[0–31])—Output..7-77.2.3.1.2 Address Bus (A[0–31])—Input.7-77.2.3.2 Address Bus Parity (AP[0–3]) 7-87.2.3.2.1 Address Bus Parity (AP[0–3])—Output 7-87.2.3.2.2 Address Bus Parity (AP[0–3])—Input...7-87.2.3.3 Address Parity Error (APE)—Output..7-87.2.4 Address Transfer Attribute Signals.7-97.2.4.1 Transfer Type (TT[0–4])..7-97.2.4.1.1 Transfer Type (TT[0–4])—Output7-97.2.4.1.2 Transfer Type (TT[0–4])—Input ..7-97.2.4.2 Transfer Size (TSIZ[0–2])—Output ..7-127.2.4.3 Transfer Burst (TBST) ...7-137.2.4.3.1 Transfer Burst (TBST)—Output .7-137.2.4.3.2 Transfer Burst (TBST)—Input 7-137.2.4.4 Transfer Code (TC[0–1])—Output .7-147.2.4.5 Cache Inhibit (CI)—Output ..7-147.2.4.6 Write-Through (WT)—Output..7-147.2.4.7 Global (GBL)7-157.2.4.7.1 Global (GBL)—Output .7-157.2.4.7.2 Global (GBL)—Input .7-157.2.4.8 Cache Set Entry (CSE[0–1])—Output .7-157.2.5 Address Transfer Termination Signals7-157.2.5.1 Address Acknowledge (AACK)—Input..7-167.2.5.2 Address Retry (ARTRY)7-167.2.5.2.1 Address Retry (ARTRY)—Output.7-167.2.5.2.2 Address Retry (ARTRY)—Input 7-177.2.6 Data Bus Arbitration Signals.7-177.2.6.1 Data Bus Grant (DBG)—Input .7-177.2.6.2 Data Bus Write Only (DBWO)—Input ...7-187.2.6.3 Data Bus Busy (DBB) 7-187.2.6.3.1 Data Bus Busy (DBB)—Output ..7-187.2.6.3.2 Data Bus Busy (DBB)—Input.7-187.2.7 Data Transfer Signals 7-197.2.7.1 Data Bus (DH[0–31], DL[0–31]) 7-197.2.7.1.1 Data Bus (DH[0–31], DL[0–31])—Output..7-197.2.7.1.2 Data Bus (DH[0–31], DL[0–31])—Input.7-207.2.7.2 Data Bus Parity (DP[0–7]) 7-207.2.7.2.1 Data Bus Parity (DP[0–7])—Output 7-207.2.7.2.2 Data Bus Parity (DP[0–7])—Input.7-207.2.7.3 Data Parity Error (DPE)—Output...7-217.2.7.4 Data Bus Disable (DBDIS)—Input.7-217.2.8 Data Transfer Termination Signals .7-217.2.8.1 Transfer Acknowledge (TA)—Input..7-227.2.8.2 Data Retry (DRTRY)—Input7-227.2.8.3 Transfer Error Acknowledge (TEA)—Input7-237.2.9 System Status Signals7-237.2.9.1 Interrupt (INT)—Input...7-237.2.9.2 System Management Interrupt (SMI)—Input ..7-247.2.9.3 Machine Check Interrupt (MCP)—Input.7-247.2.9.4 Checkstop Input (CKSTP_IN)—Input 7-247.2.9.5 Checkstop Output (CKSTP_OUT)—Output...7-257.2.9.6 Reset Signals 7-257.2.9.6.1 Hard Reset (HRESET)—Input7-257.2.9.6.2 Soft Reset (SRESET)—Input 7-267.2.9.7 Processor Status Signals.7-267.2.9.7.1 Quiescent Request (QREQ) ..7-267.2.9.7.2 Quiescent Acknowledge (QACK).7-267.2.9.7.3 Reservation (RSRV)—Output 7-277.2.9.7.4 Time Base Enable (TBEN)—Input7-277.2.9.7.5 TLBI Sync (TLBISYNC) .7-277.2.10 COP/Scan Interface...7-287.2.11 Pipeline Tracking Support..7-287.2.12 Clock Signals ..7-297.2.12.1 System Clock (SYSCLK)—Input...7-307.2.12.2 Test Clock (CLK_OUT)—Output ..7-307.2.12.3 PLL Configuration (PLL_CFG[0–3])—Input .7-307.2.13 Power and Ground Signals.7-32Chapter 8System Interface Operation8.1 Overview .8-18.1.1 Operation of the Instruction and Data Caches .8-28.1.2 Operation of the System Interface8-48.1.2.1 Optional 32-Bit Data Bus Mode .8-58.1.3 Direct-Store Accesses .8-68.2 Memory Access Protocol 8-68.2.1 Arbitration Signals 8-78.2.2 Address Pipelining and Split-Bus Transactions.8-88.3 Address Bus Tenure ..8-98.3.1 Address Bus Arbitration.8-98.3.2 Address Transfer .8-118.3.2.1 Address Bus Parity8-138.3.2.2 Address Transfer Attribute Signals.8-138.3.2.2.1 Transfer Type (TT[0–4]) Signals8-138.3.2.2.2 Transfer Size (TSIZ[0–2]) Signals.8-138.3.2.3 Burst Ordering During Data Transfers.8-148.3.2.4 Effect of Alignment in Data Transfers (64-Bit Bus).8-158.3.2.5 Effect of Alignment in Data Transfers (32-Bit Bus).8-178.3.2.5.1 Alignment of External Control Instructions.8-198.3.2.6 Transfer Code (TC[0–1]) Signals ...8-208.3.3 Address Transfer Termination .8-208.4 Data Bus Tenure..8-228.4.1 Data Bus Arbitration .8-228.4.1.1 Using the DBB Signal 8-238.4.2 Data Bus Write Only.8-248.4.3 Data Transfer...8-248.4.4 Data Transfer Termination.8-258.4.4.1 Normal Single-Beat Termination 8-268.4.4.2 Data Transfer Termination Due to a Bus Error 8-298.4.5 Memory Coherency—MEI Protocol ...8-308.5 Timing Examples.8-328.6 Optional Bus Configurations ..8-388.6.1 32-Bit Data Bus Mode..8-388.6.2 No-DRTRY Mode.8-408.6.3 Reduced-Pinout Mode ..8-408.7 Interrupt, Checkstop, and Reset Signals..8-418.7.1 External Interrupts .8-418.7.2 Checkstops.8-418.7.3 Reset Inputs .8-418.7.4 System Quiesce Control Signals 8-428.8 Processor State Signals..8-428.8.1 Support for the lwarx/stwcx. Instruction Pair8-428.8.2 TLBISYNC Input 8-428.9 IEEE 1149.1-Compliant Interface .8-438.9.1 IEEE 1149.1 Interface Description8-438.10 Using Data Bus Write Only8-439.1 Dynamic Power Management ..9-19.2 Programmable Power Modes9-19.2.1 Power Management Modes ..9-39.2.1.1 Full-Power Mode with DPM Disabled.9-39.2.1.2 Full-Power Mode with DPM Enabled..9-39.2.1.3 Doze Mode 9-49.2.1.4 Nap Mode9-49.2.1.5 Sleep Mode9-59.2.2 Power Management Software Considerations9-6A.1 Instructions Sorted by Mnemonic...A-1A.2 Instructions Sorted by Opcode A-9A.3 Instructions Grouped by Functional Categories A-17A.4 Instructions Sorted by Form ..A-28A.5 Instruction Set Legend..A-39C.1 PowerPC 603 Microprocessor Hardware Considerations.. C-1C.1.1 Hardware Support for Direct-Store Accesses . C-1C.1.1.1 Extended Address Transfer Start (XATS) C-2C.1.1.1.1 Extended Address Transfer Start (XATS)—Output ... C-2C.1.1.1.2 Extended Address Transfer Start (XATS)—Input. C-2C.1.2 Direct-Store Protocol Operation C-2C.1.2.1 Direct-Store Transactions C-4C.1.2.1.1 Store Operations. C-5C.1.2.1.2 Load Operations. C-5C.1.2.2 Direct-Store Transaction Protocol Details C-6C.1.2.2.1 Packet 0 C-7C.1.2.2.2 Packet 1 C-8C.1.2.3 I/O Reply Operations C-8C.1.2.4 Direct-Store Operation Timing C-10C.1.3 CSE Signal . C-12C.1.4 PowerPC 603 Processor Bus Clock Multiplier Configuration... C-12C.1.5 PowerPC 603 Processor Cache Organization . C-13C.1.5.1 Instruction Cache Organization . C-14C.1.5.2 Data Cache Organization . C-14C.1.6 PLL Configuration (PLL_CFG[0–3])—Input. C-15C.1.7 Address Pipelining and Split-Bus Transactions.. C-15C.1.8 Data Bus Arbitration C-16C.2 PowerPC 603 Processor Software Considerations.. C-16C.2.1 Direct-Store Interface Address Translation C-16C.2.1.1 Direct-Store Segment Translation Summary Flow.. C-17C.2.1.2 Direct-Store Interface Accesses . C-18C.2.1.3 Direct-Store Segment Protection ... C-18C.2.1.4 Instructions Not Supported in Direct-Store Segments .. C-19C.2.1.5 Instructions with No Effect in Direct-Store Segments.. C-19C.2.2 Store Instruction Latency .. C-19C.2.3 Instruction Execution by System Register Unit .. C-20C.2.4 Machine Check Exception (0x00200) C-21C.2.5 Instruction Address Breakpoint Exception (0x01400). C-21C.2.6 Cache Control Instructions C-21
