资 源 简 介
MM54HC259/MM74HC2598-Bit Addressable Latch/3-to-8 Line DecoderGeneral DescripTIonThis device uTIlizes advanced silicon-gate CMOS technologyto implement an 8-bit addressable latch, designed forgeneral purpose storage applicaTIons in digital systems.The MM54HC259/MM74HC259 has a single data input (D),8 latch outputs (Q1±Q8), 3 address inputs (A, B, and C), acommon enable input (G), and a common CLEAR input. Tooperate this device as an addressable latch, data is held onthe D input, and the address of the latch into which the datais to be entered is held on the A, B, and C inputs. WhenENABLE is taken low the data flows through to the addressedoutput. The data is stored when ENABLE transiTIonsfrom low to high. All unaddressed latches will remainunaffected. With enable in the high state the device is deselected,and all latches remain in their previous state, unaffectedby changes on the data or address inputs. To eliminatethe possibility of entering erroneous data into the latches,the enable should be held high (inactive) while the addresslines are changing.If enable is held high and CLEAR is taken low all eight latchesare cleared to a low state. If enable is low all latchesexcept the addressed latch will be cleared. The addressedlatch will instead follow the D input, effectively implementinga 3-to-8 line decoder.All inputs are protected from damage due to static dischargeby diodes to VCC and ground.FeaturesY Typical propagation delay: 18 nsY Wide supply range: 2±6VY Low input current: 1 mA maximumY Low quiescent current: 80 mA maximum (74HC Series)
