资 源 简 介
The AD5332/AD5333/AD5342/AD5343 are dual 8-， 10-， and 12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 230 µA at 3 V， and feature a power-down pin， PD that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can drive the output to both supply rails， while the AD5333 and AD5342 allow a choice of buffered or unbuffered reference input. The AD5332/AD5333/AD5342/AD5343 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. The GAIN pin on the AD5333 and AD5342 allows the output range to be set at 0 V to VREF or 0 V to 2 &TImes; VREF. Input data to the DACs is double-buffered， allowing simultaneous update of mulTIple DACs in a system using the LDAC pin. An asynchronous CLR input is also provided， which resets the contents of the Input Register and the DAC Register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there unTIl valid data is written to the device. The AD5332/AD5333/AD5342/AD5343 are available in Thin Shrink Small Outline Packages （TSSOP）.
