SystemVerilog for verification

Imagine that you are given the job of building a house for someone. Whereshould you begin? Do you start by choosing doors and windows, picking outpaint and carpet colors, or selecTIng bathroom fixtures? Of course not! Firstyou must consider how the owners will use the space, and their budget, so youcan decide what type of house to build. QuesTIons you should consider are; dothey enjoy cooking and want a high-end kitchen, or will they prefer watchingmovies in the home theater room and eaTIng takeout pizza? Do they want ahome office or extra bedrooms? Or does their budget limit them to a basichouse?Before you start to learn details of the SystemVerilog language, you needto understand how you plan to verify your parTIcular design and how thisinfluences the testbench structure. Just as all houses have kitchens, bedrooms,and bathrooms, all testbenches share some common structure of stimulus generationand response checking. This chapter introduces a set of guidelines andcoding styles for designing and constructing a testbench that meets your particularneeds. These techniques use some of the same concepts as shown inthe Verification Methodology Manual for SystemVerilog (VMM), Bergeron etal. (2006), but without the base classes.The most important principle you can learn as a verification engineer is:“Bugs are good.” Don’t shy away from finding the next bug, do not hesitate toring a bell each time you uncover one, and furthermore, always keep track ofeach bug found. The entire project team assumes there are bugs in the design,so each bug found before tape-out is one fewer that ends up in the customer’shands. You need to be as devious as possible, twisting and torturing thedesign to extract all possible bugs now, while they are still easy to fix. Don’tlet the designers steal all the glory — without your craft and cunning, thedesign might never work!This book assumes you already know the Verilog language and want tolearn the SystemVerilog Hardware Verification Language (HVL). Some ofthe typical features of an HVL that distinguish it from a Hardware DescriptionLanguage such as Verilog or VHDL areConstrained-random stimulus generationFunctional coverageHigher-level structures, especially Object Oriented ProgrammingMulti-threading and interprocess communicationSupport for HDL types such as Verilog’s 4-state valuesTight integration with event-simulator for control of the designThere are many other useful features, but these allow you to create testbenchesat a higher level of abstraction than you are able to achieve with anHDL or a programming language such as C.