资 源 简 介
INTRODUCTION 7-41.0 GLOSSARY OF DATA COMMUNICATION TERMS 7-41.1 Clear to Send . . . . . . . . . . . . 7-41.2 Data Set Ready . . . . . . . . . . 7-41.3 Data Terminal Ready . . . . . . 7-41.4 Framing Error . . . . . . . . . . . . 7-41.5 Interrupt Driven I/O . . . . . . . . 7-41.6 I/O Polling . . . . . . . . . . . . . . . 7-41.7 Overrun Error . . . . . . . . . . . . 7-51.8 Parity . . . . . . . . . . . . . . . . . . 7-51.9 Parity Error . . . . . . . . . . . . . . 7-51.10 Percentage Error in Baud Rate Generation. 7-51.11 Request to Send . . . . . . . . . . 7-62.0 CONTROL REGISTERS . . . . 7-62.1 UART Control Register . . . . . 7-62.2 Baud Rate Select Register . . 7-72.3 Modem Control Register . . . . 7-83.0 STATUS REGISTERS . . . . . . 7-103.1 UART Status Register . . . . . . 7-103.2 Modem Status Register . . . . 7-114.0 TRANSMIT/RECEIVE BUFFER REGISTERS 7-114.1 Receiver Buffer Register . . . . 7-114.2 Transmitter Buffer Register . . 7-125.0 I/O MAPPED ADDRESSING . 7-125.1 I/O Mapped Addressing . . . . 7-125.2 Memory Mapped I/O . . . . . . . 7-135.3 I/O Addressing for the 82C52 7-136.0 RESET OF THE 82C52 . . . . . 7-137.0 PROGRAMMING THE 82C52 7-14
