资 源 简 介
These TTL circuits feature dual 1-line-to-4-line demultiplexerswith individual strobes and common binary-address inputsin a single 16-pin package. When both sections areenabled by the strobes, the common address inputs sequentiallyselect and route associated input data to the appropriateoutput of each section. The individual strobes permitactivating or inhibiting each of the 4-bit sections as desired.Data applied to input C1 is inverted at its outputs anddata applied at C2 is true through its outputs. The inverterfollowing the C1 data input permits use as a 3-to-8-line decoder,or 1-to-8-line demultiplexer, without external gating.Input clamping diodes are provided on these circuits to minimizetransmission-line effects and simplify system design.
