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IC Package Impedance Matching

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  • 上传时间:2021-07-07
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  • 标      签: Package IC

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Impedance Matching Techniques for VLSI Packaging Problem Statement•ReflecTIons from interconnect will limit VLSI system performance•This is caused by :1) ParasiTIcs of the Package Interconnect2) Faster RiseTImes in Off-chip Driver Circuitry Agenda1) Package Interconnect ParasiTIcs2) Proposed Solution3) Experimental Results Why is packaging limiting performance?•Today’s Package Interconnect Looks Inductive -Long interconnect paths-Large return loops
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