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ZBT SRAM Controller Reference Design for APEX II Devices
As communication systems require more low-latency, high-bandwidthinterfaces for peripheral components, designs need high-throughputmemory with efficient bus utilization. The previous generation of staticmemory types are inefficient when they frequently switch betweenreading from and writing to the memory. To address this problem, IDT,Micron, and Motorola have developed the new zero-bus turnaround(ZBT) SRAM architecture. To implement this new memory, Altera hasdeveloped a ZBT SRAM controller reference design for use withAPEXTM II devices.This application note describes the functionality of the Altera ZBTSRAM controller reference design and explains the data tree structure,along with installation, compilation, and simulation, of the design file.
