资 源 简 介
The ’AHCT594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear (SRCLR, RCLR) inputs are provided on both the shift and storage registers. A serial (QH’) output is provided for cascading purposes.
Both the shift register (SRCLK) and storage register (RCLK) clocks are posiTIve edge triggered. If both clocks are connected together, the shift register always is one count pulse ahead of the storage register.
