资 源 简 介
Field-programmable gate arrays (FPGAs) are on the verge of revoluTIonizing
digital signal processing in the manner that programmable digital signal processors
(PDSPs) did nearly two decades ago. Many front-end digital signal
processing (DSP) algorithms, such as FFTs, FIR or IIR filters, to name just
a few, previously built with ASICs or PDSPs, are now most often replaced
by FPGAs. Modern FPGA families provide DSP arithmeTIc support with
fast-carry chains (Xilinx Virtex, Altera FLEX) that are used to implement
mulTIply-accumulates (MACs) at high speed, with low overhead and low costs
[1]. Previous FPGA families have most often targeted TTL “glue logic” and
did not have the high gate count needed for DSP funcTIons. The efficient
implementation of these front-end algorithms is the main goal of this book.
At the beginning of the twenty-first century we find that the two programmable
logic device (PLD) market leaders (Altera and Xilinx) both report
revenues greater than US$1 billion. FPGAs have enjoyed steady growth
of more than 20% in the last decade, outperforming ASICs and PDSPs by
10%. This comes from the fact that FPGAs have many features in common
with ASICs, such as reduction in size, weight, and power dissipation,
higher throughput, better security against unauthorized copies, reduced device
and inventory cost, and reduced board test costs, and claim advantages
over ASICs, such as a reduction in development time (rapid prototyping),
in-circuit reprogrammability, lower NRE costs, resulting in more economical
designs for solutions requiring less than 1000 units. Compared with
PDSPs, FPGA design typically exploits parallelism, e.g., implementing multiple
multiply-accumulate calls efficiency, e.g., zero product-terms are removed,
and pipelining, i.e., each LE has a register, therefore pipelining requires no
additional resources.
Another trend in the DSP hardware design world is the migration from
graphical design entries to hardware description language (HDL). Although
many DSP algorithms can be described with “signal flow graphs,” it has been
found that “code reuse” is much higher with HDL-based entries than with
graphical design entries. There is a high demand for HDL design engineers
and we already find undergraduate classes about logic design with HDLs [2].
Unfortunately two HDL languages are popular today. The US west coast and
Asia area prefer Verilog, while US east coast and Europe more frequently
