资 源 简 介
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operaTIon. In the 1:1 pinout configuraTIon, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuraTIon, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits opTImized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR) output.
The SN74SSTU32866 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.
The SN74SSTU32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2-D3, D5-D6, D8-D25 when C0 = 0 and C1 = 0; D2-D3, D5-D6, D8-D14 when C0 = 0 and C1=1; or D1-D6, D8-D13 when C0 = 1 and C1=1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low).
