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These synchronous, presettable counters feature an internalcarry look-ahead for application in high-speed countingdesigns. The 161 and 163 are 4-bit binary counters. Thecarry output is decoded by means of a NOR gate, thus preventingspikes during the normal counting mode of operation.Synchronous operation is provided by having all flipflopsclocked simultaneously so that the outputs change coincidentwith each other when so instructed by the countenableinputs and internal gating. This mode of operationeliminates the output counting spikes which are normallyassociated with asynchronous (ripple clock) counters. Abuffered clock input triggers the four flip-flops on the rising(positive-going) edge of the clock input waveform.These counters are fully programmable; that is, the outputsmay be preset to either level. As presetting is synchronous,setting up a low level at the load input disables the counterand causes the outputs to agree with the setup data afterthe next clock pulse, regardless of the levels of the enableinput. The clear function for the 161 is asynchronous; and alow level at the clear input sets all four of the flip-flop outputslow, regardless of the levels of clock, load, or enableinputs. The clear function for the 163 is synchronous; and alow level at the clear input sets all four of the flip-flop outputslow after the next clock pulse, regardless of the levelsof the enable inputs. This synchronous clear allows thecount length to be modified easily, as decoding the maximumcount desired can be accomplished with oneexternal NAND gate. The gate output is connected to theclear input to synchronously clear the counter to all low outputs.Low-to-high transitions at the clear input of the 163 arealso permissible, regardless of the logic levels on the clock,enable, or load inputs.The carry look-ahead circuitry provides for cascading countersfor n-bit synchronous applications without additionalgating. Instrumental in accomplishing this function are twocount-enable inputs and a ripple carry output. Both countenableinputs (P and T) must be high to count, and input T isfed forward to enable the ripple carry output. The ripple carryoutput thus enabled will produce a high-level output pulsewith a duration approximately equal to the high-level portionof the QA output. This high-level overflow ripple carry pulsecan be used to enable successive cascaded stages. Highto-low-level transitions at the enable P or T inputs of the 161through 163 may occur, regardless of the logic level on theclock.
