资 源 简 介
The SN54LVC374A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operaTIon, and the SN74LVC374A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operaTIon.
These devices feature 3-state outputs designed specifically for driving highly capaciTIve or relaTIvely low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state.
