资 源 简 介
The EL4585 is a PLL (Phase Lock Loop) sub-system,designed for video applicaTIons and also suitable for generalpurpose use up to 36MHz. In video applicaTIons, this devicegenerates a TTL/CMOS-compaTIble pixel clock (CLK OUT)which is a mulTIple of the TV horizontal scan rate and phaselocked to it.The reference signal is a horizontal sync signal, TTL/CMOSformat, which can be easily derived from an analogcomposite video signal with the EL4583 sync separator. Aninput signal to “coast” is provided for applications whereperiodic disturbances are present in the reference videotiming such as VTR head switching. The lock detector outputindicates correct lock.The divider ratio is four ratios for NTSC and four similarratios for the PAL video timing standards by externalselection of three control pins. These four ratios have beenselected for common video applications including 8FSC,6FSC, 27MHz (CCIR 601 format) and square pictureelements used in some workstation graphics. To generate4FSC, 3FSC, 13.5MHz (CCIR 601 format) etc., use theEL4584, which does not have the additional divide-by-twostage of the EL4585.
