资 源 简 介
The SN74FB1653 contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. The device is designed specifically to be compaTIble with IEEE Std 1194.1-1991 (BTL).
The A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B port when the A-port output enable (OEA) is high. When OEA is low or when VCC(5 V) typically is less than 2.5 V, the A outputs are in the high-impedance state.
The B port operates at BTL signal levels. The open-collector B ports are specified to sink 100 mA. Two output enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or VCC(5 V) typically is less than 2.
