资 源 简 介
Refer to the Transmitter data path in the data sheet. The status bitTRSR[7] is set when the Tx shift register is empty and no othercharacters (from the TxFlFO special char. or Sync char.) are waitingto fill it. There can be a one bit time delay due to the Data Encoderafter the Tx SR is empty and before the last bit of the character isseen on the TxD pin. The TEOM command causes the FCS to besent after the next character put into the Tx FIFO is sent. The CRCgeneration takes place after the Tx SR, so TRSR[7] will be set afterthe FlFOed character is serialized but before FCS is sent. Anotherstatus bit, Frame Complete, TRSR[5] is set when transmission ofthe FCS begins.
