资 源 简 介
The SN75LVDS83B FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage DifferenTIal Signaling (LVDS) line drivers in a single integrated circuit. These funcTIons allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compaTIble receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.
When transmitTIng, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially.
