资 源 简 介
These octal bus transceivers are designed specifically for low-voltage (3.3-V) VCC operaTIon, but with the capability to provide a TTL interface to a 5-V system environment.
These devices are designed for asynchronous communicaTIon between data buses. They transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direcTIon-control (DIR) input. The output-enable (OE) input can be used to disable the devices so the buses are effecTIvely isolated.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot.
