首页| 行业标准| 论文文档| 电子资料| 图纸模型
购买积分 购买会员 激活码充值

您现在的位置是:团子下载站 > 其他 > SN74AUC1G74,PDF(Hex/Quadruple

SN74AUC1G74,PDF(Hex/Quadruple

  • 资源大小:830
  • 上传时间:2021-12-20
  • 下载次数:0次
  • 浏览次数:22次
  • 资源积分:1积分
  • 标      签: Flip-Flops

资 源 简 介

These posiTIve-edge-triggered flip-flops uTIlize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR) input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. InformaTIon at the data (D) inputs meeTIng the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits.
VIP VIP